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Abstract

A logic simulation monitoring system to verify a test stimulus set and generate a test vector set for use on an Automatic Test Equipment (ATE) device during manufacturing tests. The simulation monitor executes unobtrusively as part of the logic simulation to monitor the logic simulation's real time signal activity including contention checks, output strobe margins, and ATE compatibility checks, in addition to extracting the appropriate signal response or vector resulting from a given stimulus. The simulation monitor comprises at least one simulation monitor code block generated from a combination of values from an integrated circuit parameter file and at least one code block template. Output from the simulation monitor includes a report of the contention errors and input signal errors, and a test vector set comprised of the input test stimulus set used with the logic simulation and the stimulus responses resulting from the logic simulation all in an ATE compatible and ready to use format.

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First Claim