US Patent No: 5,920,712

Number of patents in Portfolio can not be more than 2000

Emulation system having multiple emulator clock cycles per emulated clock cycle

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Abstract

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An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit. The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CADENCE DESIGN SYSTEMS, INC.SAN JOSE, CA1540

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kuijsten, Han Oakland, CA 3 145

Cited Art Landscape

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (8)
5,475,830 Structure and method for providing a reconfigurable emulation circuit without hold time violations 94 1992
5,352,123 Switching midplane and interconnection system for interconnecting large numbers of signals 89 1992
5,452,239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system 249 1993
5,448,522 Multi-port memory emulation using tag registers 30 1994
5,452,231 Hierarchically connected reconfigurable logic assembly 138 1994
5,551,013 Multiprocessor for hardware emulation 169 1994
5,448,496 Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system 107 1994
5,477,475 Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus 62 1994
 
QUICKTURN DESIGN SYSTEMS, INC. (7)
4,697,241 Hardware logic simulator 107 1985
4,914,612 Massively distributed simulation engine 80 1988
5,109,353 Apparatus for emulation of electronic hardware system 182 1988
5,036,473 Method of using electronically reconfigurable logic circuits 269 1989
5,114,353 Multiple connector arrangement for printed circuit board interconnection 23 1991
5,259,006 Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like 108 1991
5,329,470 Reconfigurable hardware emulation system 137 1993
 
MENTOR GRAPHICS CORPORATION (5)
4,527,249 Simulator system for logic design validation 107 1982
4,769,817 Concurrent fault simulation for logic designs 57 1986
4,787,061 Dual delay mode pipelined logic simulator 55 1986
4,787,062 Glitch detection by forcing the output of a simulated logic device to an undefined state 40 1986
5,126,966 High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs 49 1990
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (4)
4,306,286 Logic simulation machine 174 1979
4,357,678 Programmable sequential logic array mechanism 35 1979
4,656,580 Logic simulation machine 112 1982
4,862,347 System for simulating memory arrays in a logic simulation machine 121 1986
 
KABUSHIKI KAISHA TOSHIBA (2)
5,345,580 Microprocessor device and emulator device thereof 51 1991
5,572,710 High speed logic simulation system using time division emulation suitable for large scale logic circuits 81 1993
 
NCR CORPORATION (2)
4,695,968 Digital system simulation method and apparatus having improved sampling 31 1984
4,725,971 Digital system simulation method and apparatus 47 1984
 
STEP ENGINEERING, A CORP. OF CA (2)
4,782,461 Logical grouping of facilities within a computer development system 40 1984
5,321,828 High speed microcomputer in-circuit emulator 189 1991
 
CREDENCE SYSTEMS CORPORATION (1)
5,475,624 Test generation by environment emulation 74 1992
 
DIGICOURSE, INC. (1)
5,031,129 Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same 24 1989
 
FUJITSU PERIPHERALS LIMITED (1)
5,386,550 Pseudo-LSI device and debugging system incorporating same 17 1993
 
GENERAL DYNAMICS DECISION SYSTEMS, INC. (1)
4,587,625 Processor for simulating digital structures 66 1983
 
HITACHI, LTD. (1)
4,972,334 Automatic generation method of a simulation program for numerically solving a partial differential equation according to a boundary-fitted method 30 1988
 
MEGACHIPS CORPORATION (1)
5,437,037 Simulation using compiled function description language 51 1993
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
5,084,824 Simulation model generation from a physical data base of a combinatorial circuit 141 1990
 
NEC ELECTRONICS CORPORATION (1)
4,879,646 Data processing system with a pipelined structure for editing trace memory contents and tracing operations during system debugging 63 1987
 
PIE DESIGNS SYSTEMS, INC. (1)
5,425,036 Method and apparatus for debugging reconfigurable emulation systems 245 1992
 
RENESAS ELECTRONICS AMERICA, INC. (1)
5,331,571 Testing and emulation of integrated circuits 103 1992
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,329,471 Emulation devices, systems and methods utilizing state machines 234 1993
 
The Boeing Company (1)
4,583,169 Method for emulating a Boolean network system 26 1983
 
THOMSON COMPOSANTS MILITAIRES ET SPATIAUX A CORP. OF FRANCE (1)
5,396,498 Integrated circuit with peripheral test controller 21 1991
 
UNISYS CORPORATION (1)
4,819,150 Array for simulating computer functions for large computer systems 20 1985
 
VLSI TECHNOLOGY, INC. (1)
5,068,812 Event-controlled LCC stimulation 36 1989
 
ZOATRAM MGMT. LIMITED LIABILITY COMPANY (1)
5,377,123 Programmable logic device 29 1992

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
TABULA, INC. (32)
7,530,044 Method for manufacturing a programmable system in package 3 2005
7,788,478 Accessing multiple user states concurrently in a configurable IC 16 2006
7,550,991 Configurable IC with trace buffer and/or logic analyzer functionality 20 2006
7,548,085 Random access of user design states in a configurable IC 20 2006
7,512,850 Checkpointing user design states in a configurable IC 24 2006
7,492,186 Runtime loading of configuration data in a configurable IC 23 2006
8,412,990 Dynamically tracking data values in a configurable IC 2 2007
8,069,425 Translating a user design in a configurable IC for debugging the user design 10 2007
7,839,162 Configurable IC with deskewing circuits 15 2007
7,652,498 Integrated circuit with delay selecting input selection circuitry 28 2007
7,595,655 Retrieving data from a configurable IC 24 2007
7,579,867 Restructuring data from a trace buffer of a configurable IC 18 2007
7,501,855 Transport network for a configurable IC 21 2007
7,936,074 Programmable system in package 2 2007
7,548,090 Configurable IC with packet switch network 21 2008
7,696,780 Runtime loading of configuration data in a configurable IC 26 2008
8,201,124 System in package and method of creating system in package 3 2008
7,728,617 Debug network for a configurable IC 17 2008
8,525,548 Trigger circuits and event counters for an IC 2 2008
7,973,558 Integrated circuit with delay selecting input selection circuitry 11 2009
8,479,069 Integrated circuit (IC) with primary and secondary networks and device containing such an IC 2 2010
8,115,510 Configuration network for an IC 12 2010
8,067,960 Runtime loading of configuration data in a configurable IC 11 2010
8,072,234 Micro-granular delay testing of configurable ICs 10 2010
8,433,891 Accessing multiple user states concurrently in a configurable IC 2 2010
8,143,915 IC with deskewing circuits 11 2010
8,295,428 Trigger circuits and event counters for an IC 6 2011
8,536,713 System in package with heat sink 0 2011
8,429,579 Translating a user design in a configurable IC for debugging the user design 3 2011
8,598,909 IC with deskewing circuits 2 2012
8,760,193 Configurable storage elements 0 2012
8,755,484 Trigger circuits and event counters for an IC 0 2012
 
CADENCE DESIGN SYSTEMS, INC. (11)
6,141,636 Logic analysis subsystem in a time-sliced emulator 16 1997
7,043,417 High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory 2 2000
7,738,398 System and method for configuring communication systems 1 2004
7,738,399 System and method for identifying target systems 1 2004
7,739,093 Method of visualization in processor based emulation system 1 2005
7,721,036 System and method for providing flexible signal routing and timing 4 2005
7,640,155 Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications 5 2005
7,606,697 System and method for resolving artifacts in differential signals 0 2005
7,440,866 System and method for validating an input/output voltage of a target system 3 2005
7,555,424 Method and apparatus for rewinding emulated memory circuits 1 2006
8,595,683 Generating user clocks for a prototyping environment 0 2012
 
MENTOR GRAPHICS (HOLDING) LTD. (2)
6,947,882 Regionally time multiplexed emulation system 6 1999
7,098,688 Regionally time multiplexed emulation system 4 2003
 
ALTERA CORPORATION (1)
7,181,384 Method and apparatus for simulating a hybrid system with registered and concurrent nodes 1 2004
 
INTEGRATED DEVICE TECHNOLOGY, INC. (1)
6,226,756 Apparatus and method for providing a common system interface for processors 3 1998
 
LSI LOGIC CORPORATION (1)
6,625,572 Cycle modeling in cycle accurate software simulators of hardware modules for software/software cross-simulation and hardware/software co-simulation 15 1999
 
MENTOR GRAPHICS CORPORATION (1)
7,379,859 Emulator with switching network connections 2 2001
 
RAVESIM, INC. (1)
6,279,146 Apparatus and method for verifying a multi-component electronic design 48 1999
 
TEXAS INSTRUMENTS INCORPORATED (1)
7,590,912 Using a chip as a simulation engine 1 2006
 
Other [Check patent profile for assignment information] (1)
8,788,987 Rescaling 0 2011

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