Methods and apparatus for generating test vectors and validating ASIC designs
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United States of America Patent
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Jul 6, 1999
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N/A
app pub date -
Jul 9, 1997
filing date -
Jul 9, 1997
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Expired
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Abstract
Methods and apparatus for generating test vectors for use in testing ASIC designs at both the functional and circuit levels, and for comparing the results of functional level and circuit level tests, employ a set of software tools to facilitate generating test vectors and to compare results of simulation at the functional level with results of simulation at the synthesized circuit level. The software tool set includes a preprocessor program which reads source files and produces skeleton test vector files, a compiler program for compiling the test vector files, and an output comparison program for comparing functional level test results with circuit simulation level test results.
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