Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device
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United States of America Patent
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Jul 13, 1999
Grant Date -
N/A
app pub date -
Dec 23, 1997
filing date -
Dec 23, 1997
priority date (Note) -
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Abstract
A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.
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