Parallel synchronous header correction machine for ATM
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 13, 1999
Grant Date -
N/A
app pub date -
Feb 24, 1998
filing date -
Feb 24, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An error correction circuit for an ATM header of an ATM cell uses a sequence of synchronous comparator circuits to generate a correction mask. The sequence of comparators, when used in a processor having a 32-bit bus, provide for near minimum processing delay at an ATM node. The error correction circuit also provides error status flags for an ATM cell processor, allowing for the processor to discard ATM cells with multiple errors.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully