Apparatus for sampling instruction operand or result values in a processor pipeline
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United States of America Patent
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Jul 13, 1999
Grant Date -
N/A
app pub date -
Nov 26, 1997
filing date -
Nov 26, 1997
priority date (Note) -
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Abstract
An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a particular selected instruction. Values of results computed during the processing of the particular selected instruction are recorded in a sampling record along with state information identifying the particular selected instruction. Software is informed whenever the particular selected instruction leaves the pipeline to read the recorded values and state information.
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