Method for achieving low capacitance diffusion pattern filling
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United States of America Patent
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Jul 13, 1999
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N/A
app pub date -
May 6, 1997
filing date -
May 6, 1997
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Abstract
An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the active diffusion regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.
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