Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
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United States of America Patent
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Jul 13, 1999
Grant Date -
N/A
app pub date -
Oct 29, 1996
filing date -
Oct 29, 1996
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Abstract
A MOSFET device is formed on a P- doped semiconductor substrate with an N-well formed therein, with a pair of isolation regions formed in the N-well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.
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