Consistent packet switched memory bus for shared memory multiprocessors
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United States of America Patent
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Jul 13, 1999
Issued Date -
N/A
app pub date -
Jan 27, 1994
filing date -
Nov 30, 1990
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Abstract
A shared memory multiprocessor having a packet switched bus for transferring data between a plurality processors, I/O devices, cache memories and main memory employs a bus protocol which permits multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.
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