Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer
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United States of America Patent
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-
Jul 20, 1999
Grant Date -
N/A
app pub date -
Oct 22, 1997
filing date -
Oct 31, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor chip has such a structure as to have first connection electrodes formed at its upper circumferential edge portion and each exposed over a corresponding opening in a protective layer. An insulating layer is formed on the semiconductor chip except at each opening in the protective layer. Interconnect lines of an electroless-plated layer are formed on the first connection electrode. Solder bumps are formed on second connection electrodes formed together with the interconnect lines.
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