Importance

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Abstract

A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted. When the clock signal is de-asserted, the capacitor is allowed to charge, and an op-amp detects when the capacitor voltage exceeds a reference voltage and asserts an output signal. The reference voltage is also provided using a current source, so the transition delay is independent of changes in the power supply voltage. The clock frequency detector provided herein has a high precision with respect to process variation. A consistent frequency detection performance is achieved which is insensitive to changes in power supply voltage. This advantageously provides microprocessors with an added degree of reliability as higher circuit densities and lower supply voltages are pursued.

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First Claim