Synchronous clock generator including a delay-locked loop signal loss detector
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 20, 1999
Grant Date -
N/A
app pub date -
Aug 29, 1997
filing date -
Aug 29, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A loss of signal detector for use with a delay-locked loop of the type which produces a plurality of output signals in response to a clock signal is comprised of a first monitor for receiving a first one of the plurality of output signals from the delay-locked loop. The second monitor receives a second one of the plurality of output signals from the delay-locked loop. The first and second signals are preferably, but not necessarily, in quadrature with respect to one another. Each of the monitors is clocked with a clock signal and the inverse of the clock signal. A plurality of logic gates is responsive to the first and second monitors for producing an output signal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully