Apparatus for saving power consumption in semiconductor memory devices
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United States of America Patent
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Jul 20, 1999
Grant Date -
N/A
app pub date -
Dec 30, 1997
filing date -
Dec 31, 1996
priority date (Note) -
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Importance
Abstract
A power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected. The apparatus includes an input latch as a latch control circuit for preferentially latching a clock signal and a chip selection signal and outputting the latched signals as a control signal for controlling latch circuits.
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