Importance

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Abstract

A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.

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First Claim