Method and apparatus for half pixel SAD generation utilizing a FIFO based systolic processor
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United States of America Patent
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Jul 27, 1999
Grant Date -
N/A
app pub date -
Jan 3, 1997
filing date -
Jan 3, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A novel apparatus for and method of calculating the SAD values for half pixels is disclosed. The invention interpolates, in a serial fashion, half pixel values from full pixels contained in a search window. These half pixels ale then compared with pixels in a template macro block. The differences are then generated and accumulated in registers. The search window and template macro block pixels are shifted into FIFOs whereby a plurality of adders generates half pixel values. Latches are used to store and delay the half pixel values for input to a bank of subtractors. The subtractors calculate the differences between the interpolated half pixels and the template macro block pixels. The output of the subtractors are accumulated resulting in eight SAD values.
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