Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
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United States of America Patent
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Aug 3, 1999
Issued Date -
N/A
app pub date -
Nov 5, 1996
filing date -
Apr 6, 1990
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Abstract
A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.
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