Importance

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Abstract

In order to provide an associative memory having a low power consumption, for which data reading/writing can be performed and for which the operational speed is not decreased even during the forming of a large word, a memory cell array of b bits.times.w words is constituted by m.times.b columns and w/m rows (where m is an integer of 2 or greater). Provided are m data match signal lines for each row in the memory cell array, and in the same row of the memory cell arrays for individual bits, m memory cells are connected to m different data match signal lines. A bit line pair used for transmitting information to a memory circuit is separated from a data search line pair used for transmitting information to a comparator. The data search line is disposed on either side of a memory cell, so that adjacent memory cells for each bit in the same row of the memory cell can employ in common one of the data search line pairs located between their memory cells.

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First Claim