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Abstract

A programmable controller includes a pipeline stage having a first stage IF for executing instruction fetching operations, a second stage ID/RF for decoding the instruction and for fetching data from a general-purpose register, a third stage EX for executing arithmetic and logic operations, data address calculations, or calculation of the effective address of a target branch, a fourth stage MEM for accessing to data memory, and a fifth stage WB/BPU for executing bit operations, writing operations with respect to the general-purpose register, or branching operations, are executed in a pipelined manner. Simplification of hardware and control, and facilitation of formation of a pipeline into multiple stages are realized as a result of a pipeline structure being formed into a unified instruction structure.

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First Claim