Multiple writes per a single erase for a nonvolatile memory

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5936884
SERIAL NO

08685939

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.m adjacent levels of the memory cell. An m bit value is then read by sensing the group of 2.sup.m adjacent levels identified by the group indicator.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hasbun, Robert N Shingle Springs, CA 55 3516
Janecek, Frank P London, GB 2 111

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation