Dual level wordline clamp for reduced memory cell current
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United States of America Patent
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Aug 10, 1999
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app pub date -
Jun 15, 1998
filing date -
Dec 18, 1996
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Abstract
The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.
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