Importance

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Abstract

The invention relates to a phase-locked loop delivering a recovered clock signal from a reference clock signal F.sub.ref in which some transitions are missing. The loop includes a first divide-by-M frequency divider receiving the clock F.sub.ref and delivering a signal of frequency F.sub.ref /M; a phase comparator providing a phase error signal from the signal of frequency F.sub.ref /M, and the output signal from a second divide-by-M frequency divider; a divide-by-K frequency divider providing a signal of frequency F.sub.k from a local oscillator signal of frequency F.sub.oL receiving the phase error signal as a control signal; an adder-counter of the division ratio p/q receiving the local oscillator signal of frequency F.sub.oL and delivering a signal of frequency F.sub.o equal to F.sub.oL *p/q; a mixer delivering a signal of frequency F.sub.n equal to F.sub.o -F.sub.k on the basis of signal of frequency F.sub.k and the signal of frequency F.sub.o ; and a divide-by-N frequency divider synchronized by F.sub.oL, receiving the signal of frequency F.sub.n, and delivering a recovered clock to the second divide-by-M frequency divider.

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First Claim