High-speed, parallel, processor architecture for front-end electronics, based on a single type of ASIC, and method use thereof
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United States of America Patent
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Aug 10, 1999
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app pub date -
Feb 15, 1996
filing date -
Feb 11, 1993
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Abstract
An array of processors, each having a data input for receiving raw data, and other data input ports for receiving data for other processors of the plurality. Each processor processes data according to an algorithm programmed therein, and either passes the processed data or raw data to the other processors. By using a three dimensional array of processors, data from a large number of inputs can be processed in a high speed manner and funneled to a smaller number of outputs. An efficient microcode and processor architecture allows high speed processing of data using very few clock cycles, and can pass raw data to another processor in a single clock cycle.
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