Method and apparatus for internally caching the minimum and maximum XY pixel address values in a graphics subsystem
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United States of America Patent
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Aug 17, 1999
Grant Date -
N/A
app pub date -
May 7, 1997
filing date -
May 7, 1997
priority date (Note) -
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Abstract
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes an address tracking logic circuit tracks the rendering primitive to determine the minimum and maximum XY addresses of the rendered primitive. By tracking of the XY address, the graphics processor is able to internally cache only modified portions of the rendered primitive thereby improving the graphics processor's access cycle to the modified data. Accordingly, the graphics processor's memory bandwidth requirements is reduced.
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