Synchronous clock generator including a false lock detector
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United States of America Patent
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Aug 17, 1999
Grant Date -
N/A
app pub date -
Aug 29, 1997
filing date -
Aug 29, 1997
priority date (Note) -
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Abstract
A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.
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