Method for manufacturing known good die array having solder bumps
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United States of America Patent
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Aug 17, 1999
Issued Date -
N/A
app pub date -
May 12, 1997
filing date -
Jan 10, 1994
priority date (Note) -
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Abstract
A method for manufacturing a known good die array('KGD' array ), which includes the steps of: (a) forming a plurality of circuit patterns, and bonding pads to match solder bumps on a wafer; (b) providing solder bumps on the bonding pads; (c) forming metal layers for wire-bonding on the solder bumps; (d) dividing the wafer having metal layers into respective individual circuit pattern unit dies; (e) holding at least one die in a die holder for testing; (f) wire-bonding circuit contacts of the die holder with the metal layers using wires; (g) testing the die which is electrically interconnected with the die holder; and (h) removing simultaneously the metal layer on the solder bumps for wire bonding and the wires from the die to give a known good die array having solder bumps.
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