Importance

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Abstract

The present invention aims at providing a data processing system which can realize a variety of process. A secondary memory cassette 31 includes a connector 32 which can be connected to both a primary memory cassette 21 or a processing device body, and address transfer circuit 39 which judges whether the connector has been connected to the primary memory cassette 21 based upon the connection state of the connector and outputs an address transfer signal, and a memory 38 which outputs data corresponding to the address transfer signal and the address signal supplied from connector 32. The primary memory cassette 21 includes a mask ROM 28, a connector 22 for connection with the processing device body, and a connector 24 which can be connected with the secondary memory cassette 31. A predetermined pin of connector 24 is connected to a ground. When primary memory cassette 21 is connected with secondary memory cassette 31, signal Sa becomes level L, so that address transfer circuit 39 changes the memory allocation of ROM 38.

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First Claim