Digital signal processor architecture optimized for performing fast Fourier Transforms
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United States of America Patent
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Aug 24, 1999
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app pub date -
Jun 30, 1997
filing date -
Jun 30, 1997
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Abstract
A digital signal processor architecture particularly adapted for performing fast Fourier Transform algorithms efficiently. The architecture comprises dual, parallel multiply and accumulate units in which the output of the multiplier circuit portion of each MAC is cross-coupled to an input of the adder unit of the other MAC as well as to an input of the adder unit of the same MAC to which the multiplier belongs.
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