FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines
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United States of America Patent
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Aug 24, 1999
Grant Date -
N/A
app pub date -
Mar 20, 1997
filing date -
Mar 20, 1997
priority date (Note) -
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Abstract
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some buffered interconnect lines are bidirectional, and others are unidirectional. A carefully selected mixture of unidirectional and bidirectional lines provides a balance of flexibility, silicon area, and performance.
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