Importance

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Abstract

A circuit and method for preventing latch-up in a CMOS semiconductor device. In an n-type substrate and p-type well region semiconductor, the method comprises the steps of pulling V.sub.sub of the substrate terminal to V.sub.CC and pulling V.sub.well of the well region terminal to V.sub.SS when V.sub.CC is below a predetermined voltage V.sub.det, and releasing V.sub.CC and V.sub.SS from respective substrate and well region terminals when V.sub.CC rises above V.sub.det. Or, if V.sub.CC is above both V.sub.det and V.sub.sub then pulling V.sub.sub to V.sub.CC and pulling V.sub.well to V.sub.SS. If V.sub.CC is above V.sub.det but below V.sub.sub then pulling V.sub.well below V.sub.SS. Similarly, in a p-type substrate and n-type well region semiconductor, the method comprises the steps of pulling V.sub.sub of the substrate terminal to V.sub.SS and pulling V.sub.well of the well region terminal to V.sub.CC when V.sub.CC is below a predetermined voltage V.sub.det, and releasing V.sub.SS and V.sub.CC from respective substrate and well region terminals when V.sub.CC rises above V.sub.det. Or, if V.sub.CC is above both V.sub.det and V.sub.sub then pulling V.sub.sub to V.sub.SS and V.sub.well to V.sub.CC. If V.sub.CC is above V.sub.det but below V.sub.sub then pulling V.sub.sub below V.sub.SS.

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First Claim