Direct memory access unit having a definable plurality of transfer channels
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United States of America Patent
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Aug 31, 1999
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N/A
app pub date -
Sep 12, 1997
filing date -
Sep 12, 1997
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Abstract
Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.
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