FPGA input output buffer with registered tristate enable
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United States of America Patent
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Aug 31, 1999
Issued Date -
N/A
app pub date -
Apr 8, 1997
filing date -
Aug 3, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.
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