Clocked flip flop circuit with built-in clock controller and frequency divider using the same
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United States of America Patent
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Aug 31, 1999
Grant Date -
N/A
app pub date -
Mar 31, 1998
filing date -
Mar 31, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A clocked master slave flip flop circuit includes a current mirror circuit with a pair of field effect transistors serving as a constant current source, and the field effect transistors are gated by a clock signal and a complementary clock signal; and the clocked master slave flip flop circuit further includes a built-in logic circuits achieving logic functions inverse to each other, and one the built-in logic circuits and the other field effect transistor are connected in series of one of the field effect transistors and in parallel to the other field effect transistor; the logic circuits are responsive to a clock control signal so as to enable the constant current source, and causes the clocked master slave flip flop circuit to change or maintain a data bit stored therein.
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