US Patent No: 5,946,244

Number of patents in Portfolio can not be more than 2000

Delay-locked loop with binary-coupled capacitor

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Abstract

A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MOSAID TECHNOLOGIES INCORPORATEDOTTAWA1227

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Manning, Troy A Meridian, ID 229 4814

Cited Art

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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
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