Semiconductor wafer evaluating method and semiconductor device manufacturing method
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United States of America Patent
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Aug 31, 1999
Grant Date -
N/A
app pub date -
Jan 16, 1998
filing date -
Jun 2, 1997
priority date (Note) -
Expired
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Abstract
An object is to obtain a semiconductor wafer evaluation method and a semiconductor device manufacturing method having a reduced turn-around time and requiring no process apparatus and no dielectric breakdown characteristic evaluation device in evaluation of the dielectric breakdown characteristic of the oxide film. A sample wafer (1) is etched by using an SC-1 solution bath (2) to change process defects caused in the fabrication process including mirror polishing into pits. The number of pits is detected with a dust particle inspection system, and the dielectric breakdown characteristic of the sample wafer 1 can be evaluated by using the number of detected pits and previously obtained relations between the number of pits and the dielectric breakdown characteristic.
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