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Abstract

A method of designing a mask pattern to be formed in a mask used for manufacturing an integrated circuit by forming a pattern in a first layer deposited on a substrate, on the basis of lithography to which said mask is applied, then depositing a second layer on the substrate including the patterned first layer and flattening the second layer by a chemical/mechanical polishing process, the method comprising the steps of (A) dividing the mask pattern into meshes having the form of a lattice and having a predetermined size, and determining pattern area ratios .alpha..sub.0 (i,j) of the meshes(i,j), respectively, (B) determining an average pattern area ratio .beta.(i,j) within a predetermined region including a mesh(i,j) as the central point in the predetermined region with regard to each of all the meshes in the mask pattern, and (C) providing a dummy pattern to each of the meshes(i,j) which have been found in the step (B) to have the average pattern area ratios .beta.(i,j) smaller than a predetermined value.

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First Claim