Voltage clamping method and apparatus for dynamic random access memory devices
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United States of America Patent
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Sep 7, 1999
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N/A
app pub date -
Oct 30, 1998
filing date -
Oct 30, 1998
priority date (Note) -
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Abstract
A circuit for clamping the voltage appearing on the bit lines of a dynamic random access memory (DRAM) device so that the voltage thereon is maintained above the low reference voltage source. The circuit includes pull-up devices connected to the bit lines of the DRAM device. The pull-up devices are active only when pull-down devices connected to the bit lines pull some of the bit lines towards the low reference voltage level.
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