Method to back annotate programmable logic device design files based on timing information of a target technology
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United States of America Patent
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Sep 7, 1999
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N/A
app pub date -
Apr 18, 1996
filing date -
Apr 18, 1996
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Abstract
One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.
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