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Abstract

An interpolated lookup table circuit includes an input port for receiving an input signal having a first plurality of bits (N bits) including a first portion (Q bits) and a second portion (N-Q bits), a lookup table (LUT) having a plurality of entries wherein each of the plurality of entries has a second plurality of bits including a third portion (V bits) and a fourth portion (D bits), selection means operatively coupled to the input port and responsive to at least the first portion of the input signal which selects one of the plurality of LUT entries based on the first portion of the lookup table input signal. The interpolated LUT circuit also includes a combiner operatively coupled to the input port and the LUT wherein the combiner combines the second portion of the input signal, the fourth portion of the selected LUT entry, and the third portion of the second plurality of bits of the selected LUT entry to provide an interpolated LUT output signal which is input to a rounding circuit wherein the interpolated LUT output signal is rounded or truncated to provide a rounded interpolated LUT output signal.

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First Claim