Roving range control to limit receive PLL frequency of operation
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United States of America Patent
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Sep 14, 1999
Grant Date -
N/A
app pub date -
Mar 25, 1998
filing date -
Mar 25, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.
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