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Abstract

A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches to isolate the computer data bus from the memory chips. The apparatus includes one or more multi-sided memory boards with etched leads, lands and feed-through. The memory chips may be mounted on either one side, or both sides of each board. Connection between the memory board and the mother board are made by means of a comb of contact fingers, or edge-connector which mates with a connector on the mother board. The data lines and address lines of the computer bus are distinct from each other, and routed to the memory board via the edge connector. A set of CMOS TTL or FET switches are located adjacent to the comb, and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU, controller or other decoding means located on the motherboard. As a result, only the memory chips actually required for the memory access are switched on, so that the other memory chips are isolated from the data bus. Because of this isolation, the capacitance of the non-switched components is not seen by the data bus, resulting in a lower overall capacitance, and a higher inherent memory access.

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First Claim