Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer
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United States of America Patent
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Sep 14, 1999
Grant Date -
N/A
app pub date -
Dec 29, 1997
filing date -
Dec 31, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.
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