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Abstract

A method and system of enabling intra-system communication between first and second microprocessors in an asynchronous transfer mode (ATM) environment includes emulating ATM segmentation and reassembly at the first microprocessor. The second microprocessor is connected to circuitry for supporting ATM communications with other systems. With respect to an inter-processor communication (IPC) from the first microprocessor to the second microprocessor, conventional ATM segmentation is emulated at the first microprocessor, thereby forming fixed-length cells having payloads representative of the IPC. ATM-compatible header information is attached to each one of the cells and transferred to the circuitry, which typically includes a segmentation and reassembly (SAR) device. The circuitry reassembles the message and forwards the IPC to the second microprocessor. With respect to an IPC directed from the second microprocessor to the first microprocessor, the message is segmented at the circuitry to form fixed-length cells having payloads representative of the message. ATM-compatible header information identifying the first microprocessor as the destination is attached to each of the cells. The cells are then transferred to the first microprocessor, where conventional ATM reassembly of the message is emulated.

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