Electrically erasable programmable nonvolatile semiconductor memory having dual operation function
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United States of America Patent
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Sep 28, 1999
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N/A
app pub date -
Feb 24, 1998
filing date -
Jul 9, 1997
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Abstract
An electrically erasable programmable nonvolatile semiconductor memory has a memory cell array having a plurality of memory cells which are placed as a matrix configuration. The memory cell array is divided into a plurality of memory cell blocks having required sizes by splitting each bit line of the memory cell array at: an optional position. This memory provides a dual operation function without complicating the circuit thereof or increasing the chip size thereof. The bit structure of each memory cell block to be divided from the memory cell array is variable.
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