Computer address translation using fast address generator during a segmentation operation performed on a virtual address
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United States of America Patent
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Sep 28, 1999
Issued Date -
N/A
app pub date -
Aug 4, 1997
filing date -
Jun 2, 1995
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Abstract
An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.
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