Configurable logic element with fast feedback paths
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United States of America Patent
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Oct 5, 1999
Issued Date -
N/A
app pub date -
Mar 24, 1997
filing date -
Feb 26, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.
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