Method of fabricating a MOS device with a localized punchthrough stopper
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 5, 1999
Grant Date -
N/A
app pub date -
Aug 5, 1997
filing date -
Aug 5, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of fabricating a MOS device with a localized punchthrough stopper. In the process, a dummy layer is employed to define a well for implanting the localized punchthrough stopper. The dummy layer is preferably made of silicon nitride, which has a high etching selectivity with respect to the oxide material forming sidewall spacers of MOS devices. The localized punchthrough stopper is formed at the boundary of the lightly-doped regions and the channel by implanting impurities through the well resulting from the removal of a portion of the dummy layer adjacent to the gate structure.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully