Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
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United States of America Patent
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Oct 12, 1999
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Dec 17, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.
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