Interface controller including hardware mechanism to handle PS/2 interface
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United States of America Patent
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Oct 12, 1999
Grant Date -
N/A
app pub date -
Mar 7, 1997
filing date -
Mar 7, 1997
priority date (Note) -
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Abstract
A controller handles host commands from a host processor and also interfaces the host processor to a serial device. Storage circuitry (e.g., a shift register) of the controller holds a predetermined plurality of data bits. State machine circuitry controls the storage circuitry for serial bit-level communication (e.g., using a PS/2 protocol) between the storage circuitry and the serial device. A processor executes code from a program memory. In particular, the program code causes the processor to detect that a host command has been received by the controller from the host processor and causes an action corresponding to the host command received. Because the processor is not involved with the serial bit-level communication between the storage circuitry and the serial device, the processor executing the software can handle host commands without affecting the serial bit-level communication.
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