Floating gate memory cell array allowing cell-by-cell erasure
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United States of America Patent
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Oct 12, 1999
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N/A
app pub date -
Nov 27, 1996
filing date -
Nov 29, 1995
priority date (Note) -
Expired
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Abstract
A non-volatile semiconductor memory device includes a plurality of memory cells. Each of the plurality of memory cells has a control gate, a source, a drain and a floating gate for storing charges. The floating gate is preferably capacitively coupled to at least one of the source and the drain. The memory device also includes a control circuit for controlling voltages that are respectively applied to the control gate, the source and the drain in order to execute an erasure operation of at least one memory cell in a 'memory cell-by-memory cell' format.
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