Importance

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Abstract

A synchronous burst access memory device fits in a standard Fast Page Mode DRAM package. The device is adapted to receive a free running system clock, a Byte Enable input (BE) and a Burst Control input (BC). The burst access memory device has an internal column address counter for burst accesses, but is capable of receiving a new column address with each clock edge in a page access to provide for random access of the memory. A data pipeline allows for high clock speeds and high data throughput. The state of the byte enable pin when the row address is latched determines whether a refresh cycle or a data access is to be performed. The BC input is also used to mask the clock input during row address strobe to column address strobe delay periods (tRCD). The clock input is used as a column address strobe after tRCD. A write enable input selects between read and write access cycles. The BC input determines whether the column address for the current cycle will be a new address latched from a source external to the memory device, or an internally generated address from the address counter.

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First Claim